A junction field-effect transistor (hereinafter referred to as JFET) has a pn junction provided on either side of a channel region where carriers are passed therethrough, and a reverse bias voltage is applied from a gate electrode to extend a depletion layer from the pn junction into the channel region to control the conductance of the channel region and carry out such an operation as switching. In particular, a lateral JFET refers to the one having a channel region through which carriers move in parallel with the surface of the device.
The carriers in the channel may be electrons (n-type) or holes (p-type). A JFET having a semiconductor substrate of SiC usually has a channel region which is an n-type impurity region. For convenience of the following description, therefore, it is supposed that carriers in the channel are electrons and accordingly the channel region is an n-type impurity region, however, it should be understood that the channel region may be a p-type impurity region.
FIG. 7 shows a cross section of a conventional lateral JFET (U.S. Pat. No. 5,264,713 entitled “Junction Field-Effect Transistor Formed in Silicon Carbide”). On a p-type SiC substrate 110, a p+-type epitaxial layer 112 is provided on which an n−-type channel layer 114 is formed. On channel layer 114, an n-type source region 116 and an n-type drain region 118 are provided on respective sides of a trench 124 located therebetween, and a source electrode 120 and a drain electrode 122 are provided respectively on the source region and the drain region. On the back surface of SiC substrate 110, a gate contact layer 130 is formed on which a gate electrode (not shown) is provided. Trench 124 is provided with its depth extending through source/drain regions 116 and 118 to enter channel layer 114. Between the bottom of trench 124 and epitaxial layer 112 of a first conductivity type, a channel C is formed in epitaxial layer 114 of a second conductivity type.
The concentration of p-type impurities in epitaxial layer 112 is higher than the concentration of the n-type in epitaxial layer 114 which includes the channel, and thus a reverse bias voltage applied to the junction extends a depletion layer toward the channel. The depletion layer then occupies the channel to prevent current from passing through the channel and accordingly cause an OFF state. Control is thus possible to cause or not to cause the channel region to be occupied by the depletion layer by adjusting the magnitude of the reverse bias current. Then, ON/OFF control of current is possible by adjusting the reverse bias voltage between, for example, the gate and source.
For ON/OFF control of a large current, it is highly desirable to reduce an ON resistance in order to decrease the power consumption, for example. If the ON resistance is reduced by increasing the thickness of the channel or the impurity concentration of the channel layer, however, a problem of deterioration in breakdown voltage performance occurs.
FIG. 8 shows the channel, source, drain and gate for illustrating a breakdown voltage performance of the lateral JFET. FIG. 9 illustrates an electric field distribution between the drain and gate at a breakdown voltage. The electric field distribution shown in FIG. 9 refers to an electric field distribution in the n-type epitaxial layer that extends from the p-type epitaxial layer to the drain electrode. Emax in FIG. 9 represents a breakdown electric field when the depletion layer has a distance W from the drain to the pn junction. Emax may be represented by expression (1) below, where q represents an elementary charge, Nd represents an n-type impurity concentration in the region from the drain electrode to the pn junction, and ∈s represents a dielectric constant of the semiconductor.Emax=qNdW/εs  (1)
With the source grounded, the drain-gate voltage is at its maximum when breakdown occurs. Accordingly, a breakdown voltage Vb, i.e., withstand voltage is represented by following expressions (2)-(4), where Vdgmax represents the maximum voltage applicable to the region between the drain and the gate, and Vgs represents a gate-source voltage necessary for causing an OFF state.Vb=Vdgmax−Vgs  (2)Vdgmax=qNdW2/(2∈s)  (3)Vgs=qNdh2/(2∈s)  (4)
There are two direct methods as described below for reducing the ON resistance. For the two methods each, it will be considered whether or not the breakdown voltage performance is enhanced, namely whether or not Vb increases.
(a) The channel thickness h is increased (without changing the impurity concentration).
Vgs increases as seen from expression (4) and accordingly Vb decreases as determined by expression (2), which means that the breakdown voltage performance is deteriorated.
(b) The n-type impurity concentration Nd in the n-type epitaxial layer including the channel is increased. (Vgs is unchanged. In other words, the n-type impurity concentration is increased while the channel thickness h is decreased.)
The n-type impurity concentration in the n-type epitaxial layer is changed to increase Emax as seen from expression (1), while W is decreased which is known from an expression (which is not shown above). Although a relation between withstand voltage Vdgmax and the n-type impurity concentration cannot be derived directly from the expressions described above, the relation may be determined as shown in FIG. 10. It is seen from FIG. 10 that withstand voltage Vdgmax decreases as the impurity concentration increases.
It is understood from the foregoing discussion that the direct decrease of the ON resistance of the lateral JFET degrades the breakdown voltage performance thereof.